This application claims the benefit of Korean Application No. 99-19020, filed May 26, 1999, in the Korean Industrial Property Office, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to the field of clock signal recovery, and more particularly, to a circuit for recovering a digital clock signal in a recording and/or reproducing apparatus of an optical disc and a method thereof.
2. Description of the Related Art
In the apparatus for recording data on and/or reproducing data from an optical disc such as a compact disc (CD) or a digital versatile disc (DVD), it is necessary to synchronize a reproduction signal with a system clock signal. A circuit which performs the synchronization process is a phase locked loop (PLL) circuit.
A PLL circuit locks a phase by generating a system clock signal through a voltage controlled oscillator (VCO). The VCO oscillates with a certain frequency with respect to a received signal, varying the frequency of the system clock signal, and locking the received signal to the varied system clock signal. In general, phase locking starts by determining whether the difference between the oscillation frequency of the VCO and the frequency of the received signal is within a predetermined range, and if not, performing frequency locking.
The conventional clock recovery circuit 90 used in an optical disc drives a PLL circuit shown in FIG. 1. The PLL circuit includes a binarization circuit 110, a frequency detector 120, a phase error detector 130, a low pass filter (LPF) 140, and a VCO 150. The analog signal read from an optical disc 100 is received by a binarization circuit 110, which compares the received signal with a binarization level, and provides a binarized signal. The binarization circuit 110 can be, for example, a comparator.
When the frequency difference received by the frequency error detector 120 is within a first predetermined range, the frequency error detector 120 receives the binarized signal and detects the difference between the frequency of the binarized signal and the frequency of the system clock signal generated by the VCO 150. The frequency error detector 120 provides the difference to the LPF 140. The LPF 140 provides a control voltage corresponding to the frequency difference to the VCO 150.
When the frequency difference is within a second predetermined range, the frequency error detector 120 does not operate. Instead, the phase error detector 130 detects the phase difference between the binarized signal and the system clock signal, and the detected phase difference is provided to the LPF 140. The LPF 140 provides the control voltage corresponding to both the frequency difference and the phase difference to the VCO 150.
The VCO 150 generates a system clock signal synchronized with the received signal according to the control voltage signal provided by the LPF 140. While not shown in FIG. 1, the VCO 150 provides the system clock signal as a driving clock signal to the frequency error detector 120 and the phase error detector 130.
Using a conventional PLL circuit, the binarization circuit 110 and the LPF 140 are both analog circuits. Since they are analog, the performance of the PLL circuit deteriorates due to noise passing through the LPF 140. In addition, it is difficult to correct the binarization level corresponding to the received signal using the binarization circuit 110. Also, using a conventional analog filter, it is difficult to properly adjust the LPF 140 to account for a multiple-speed mode. Basically, in order to correctly utilize the binarized signal, the LPF 140 must include a circuit which traces the center value of the received analog signal. Since the LPF 140 is analog, it is not possible to freely change the frequency band to account for this center value, and noise is mixed in the signal no matter how fine the filter is.
One solution has been having the binarization circuit 110 that incorporates a partial response maximum likelihood (PRML) method. Such a binarization circuit 110 has a structure that outputs a binary signal that is adjusted to the statistical characteristic of the received signal using sampled data. This sampled data is obtained by converting the analog signal into a digital signal, correcting the center value of the analog signal using the sampling value obtained by the analog-to-digital (A/D) conversion, and synchronizing the sampled data with a system clock signal using the center value of the received analog signal. However, these functions are difficult to realize using an analog structure.
In addition, when an analog LPF 140 is used to provide both the frequency error and the phase error as the control voltage of the VCO 150, it is not possible to freely change the frequency band, which mixes the noise in the signal. Therefore, an analog LPF is difficult to apply to newer optical disc products which have a high multiple speed mode.
Accordingly, it is an object of the present invention to provide a digital clock recovery circuit having a digital binarization circuit and low pass filter (LPF).
It is another object of the present invention to provide a method of correcting asymmetry of an analog signal read from an optical disc, binarizing the corrected analog signal, digital signal processing the corrected binarized signal, and recovering a system clock signal.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
To achieve the first and other objects of the present invention, there is provided a digital clock recovery circuit for recovering a system clock signal locked to a received analog signal, comprising an analog-to-digital (A/D) converter and asymmetry corrector which corrects a received signal into digital data and provides corrected digital data that is corrected by a binarization level which traces the center value of the received analog signal, a frequency error detector which detects a frequency error from the corrected digital data, a phase error detector which detects a phase error from the corrected digital data, a digital low pass filter (LPF) which provides the frequency error and the phase error as a control voltage, and a clock generator which generates a system clock signal whose frequency and phase are varied according to the control voltage and provides the system clock signal as driving clock signals of the respective elements.
To achieve the second and other objects of the present invention, there is provided a method of recovering a system clock signal locked to a received signal by a phase locked loop (PLL), comprising converting a received analog signal into digital data and providing digital data corrected by a binarization level which traces the center value of the received analog signal, detecting a frequency error from the corrected digital data, detecting a phase error from the corrected digital data, and low pass filtering the phase error and providing the low pass filtered phase error to a control voltage of the PLL together with the frequency error.